1. Field of the Invention
This invention relates to a memory device, and in more particular, to a memory device for generating a plurality of step-down voltages from an externally supplied power-supply voltage.
2. Prior Art
In order to increase the reliability and decrease the power consumption of transistors of internal circuits in a memory device such as a DRAM, or in order for stable operation of the internal circuits when the externally supplied power-supply voltages changes, the internal circuits are operated with an internal power supply voltage that is generated by stepping down and smoothing the external power-supply voltage.
In this case, when a plurality of step-down voltages are required in the memory device, a plurality of step-down circuits have been used in the memory device, and each step-down circuit directly steps down the external power-supply voltage to generate a plurality of step-down voltages. In the case of a reference level where the required step-down voltage does not require drive capability, the external power-supply voltage may be divided by resistance.
FIG. 11 is a schematic drawing of a step-down voltage generating circuit for a prior memory device. The prior step-down voltage generating circuit 19 comprises a NMOS transistor 90 for generating a first step-down voltage Vii from an external power-supply voltage Vcc, and a NMOS transistor 91 for generating a second step-down voltage Viic from the external power-supply voltage Vcc.
The drain of the NMOS transistor 90 is connected to the external power-supply voltage Vcc, and the gate is connected to the reference level Vg. The reference level Vg is set as follow, as the threshold voltage Vth of the NMOS transistor 90. EQU Vg=Vii+Vth
In addition, the first step-down voltage Vii is supplied from the source of the NMOS transistor 90 to a first internal circuit 92. Iii is the current consumed by the first internal circuit 92, and is the current flowing between the drain and source of the NMOS transistor 90.
Moreover, the drain of the NMOS transistor 91 is connected to the external power-supply voltage Vcc, and the gate is connected to the reference level Vgc. The reference level Vgc is set as follow, as the threshold voltage Vth of the NMOS transistor 91. EQU Vgc=Viic+Vth
In addition, the second step-down voltage Viic is supplied from the source of the NMOS transistor 91 to a second internal circuit 93. Iiic is the current consumed by the second internal circuit, and is the current flowing between the drain and source of the NMOS transistor 91.
FIG. 12 is a drawing showing the characteristics of the output voltage of a prior step-down voltage generating circuit. The horizontal axis shows the current consumption of the internal circuits, and the vertical axis shows the output voltage of the step-down voltage generating circuit. FIG. 12 explains the relationship between the first step-down voltage Vii and the second step-down voltage Viic when the consumed current of the internal circuits is normal or extremely low. The consumed current shown along the horizontal axis is a Log scale.
The prior step-down voltage generating circuit was designed so the internal circuits would operate normally when the first and second internal circuits consumed the normal current Iii1, Iiic1; for example when the second step-down voltage Viic is set to be less than first step-down voltage Vii (Vii1&gt;Viic). However, when the operating speed of the internal circuits drops, the consumed current Iii1 of the first internal circuit 92 that is supplied with the first step-down voltage Vii is equal to the normal value due to leaked current, and when the leak current Iiic2 of the second internal circuit 93 that is supplied with the second step-down voltage Viic is less than normal, the second step-down voltage Viic2 becomes greater than first step-down voltage Vii1 (Vii1&lt;Viic2), and there may malfunction of the second internal circuit 93 to which the second step-down voltage Viic2 is supplied.
The reason that the second step-down voltage Viic rises is as follows. When the consumed current Iiic drops, the source voltage of the transistor 91 rises and the transistor 91 is in the sub-threshold operation state where the voltage between the gate and source is less than the threshold voltage. As a result, the source voltage Viic rises to a level near the drain voltage Vcc.
For example, in a memory device where the first step-down voltage Vii is supplied to the peripheral circuits and the second step-down voltage Viic is supplied to a sense amp, the memory device is designed such that it operates normally when the voltage relationship is: EQU Vii&gt;viic
In order to suppress the consumed current in the sense amp of the cell array, which uses a large part of the consumed current of the memory device, another lower voltage Viic than vii is used for the sense amp. Here, where there is no access operation of the memory cell, such as long standby period of the memory device, or a power-down period when the entire device operation actually stops, since the consumed current of the sense amp of the cell array drops, it is not possible to maintain the aforementioned voltage relationship, resulting in the kinds of malfunction described below.
FIG. 13 shows the operating waveform when the memory cell first becomes active after the relatively long standby period, or after the power-down period. Since the consumed current Iiic is very small during the standby period of the memory device or the power-down period, the second step-down voltage Viic rises to Viic2 as shown in FIG. 12.
Therefore, the voltage of one bit line that is driven by the sense amp becomes the risen second step-down voltage Viic2. Further during the word-line drive period due to the first access, it does not drop to the prescribed voltage Viic1 by the consumed current due to data amplification of the bit line. Therefore, during the following pre-charge period, when the bit-line short signal brs becomes active and the bit lines BL, /BL are shorted, the voltage of the bit lines BL, /BL becomes 1/2 the bit-line BL voltage at that instant (Viic2 and ground potential) and becomes larger than the prior pre-charge voltage Vpr1 (1/2 of Viic1). In the operating waveform drawing of FIG. 13, when activation of the sense amp begins, the overdrive waveform wherein the drive power supply is temporarily made the first step-down voltage Vii, is shown.
When the voltage of the bit lines BL, /BL becomes high like this, the margin of the sense amp with respect to the H-level data written in the cell becomes small, and there is a possibility of malfunction when reading during the second access.
When the drive voltage of the word line WL is the step-up voltage Vpp, H level of the cell becomes the voltage of the threshold voltage subtracted from the step-up voltage Vpp (Vpp-Vth). Normally the step-up voltage is set such that Vpp-Vth=Viic. By taking the bit-line capacity to be Cb, the cell capacity to be Cs and bit-line pre-charge voltage to be Vpr, then the change in bit-line voltage dV when reading a cell of H level (Viic1) is calculated from EQU Cb.times.Vpr+Cs.times.Viic1=(Cb+Cs).times.(Vpr+dV)
to obtain: EQU dv=Cs.times.(Viic1-Vpr)/(Cb+Cs)
This potential difference dV between the pair of bit lines is detected and amplified by the sense amp. Also, from the equation above, it can be seen that when the pre-charge voltage Vpr of the bit lines becomes high, the sense amp detective margin disappears. Therefore, it is necessary that the second step-down voltage Viic does not increase even when the consumed current of the sense amp of the cell array drops during the standby period or power-down period.